Test equipment typically has a finite amount of internal memory, also called scan memory, in which to hold test patterns for a device under test (DUT). The maximum number of test patterns which will fit into scan memory are loaded at the beginning of a test operation, and then the test equipment applies the test patterns to one or more devices mounted on the test equipment. Device test coverage is increased with the application of more test patterns, while the time and cost required to test the device is decreased, when the test equipment applies the test patterns at a faster rate.
One group of integrated circuits which benefits from testing is programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs). Test programs for FPGAs typically consist of many paired test patterns: one to configure the FPGA, and another to test the functionality of the FPGA after configuration. Process technology improvements have led to denser and larger FPGAs, which has resulted in larger FPGA configuration patterns. However, these larger configuration test patterns for higher density FPGAs lead to longer test pattern load times and lower test coverage, because fewer test patterns can fit into scan memory. Further, while shorter test times can be achieved by providing test data to the device under test at a faster rate, the ability to apply the test data at a faster rate is limited by the design of the test equipment.
Accordingly, there is a need for an improved device and method of coupling test signals to a device under test which provides a more efficient use of memory and overcomes processing limitations of test equipment.